Signal and noise - electronics

SMT stencil cutting

2012-12-25T10:56:00-05:00

I've been making some SMT stencils using a Silhouette Cameo craft cutter (vinyl cutter). It's great for fast turnaround time and low materials cost, though the quality is not as high as a laser-cut stainless-steel stencil. Still, they're useful down to 0.5 mm pitch and 0201, and possibly a little better, and that's good enough for many applications.

Here's a stencil cut by the Cameo. The partial QFP footprint is 0.5 mm pitch and the smallest discretes are 0402.

gerber2graphtec examples/test_0.5mm_0402.gbr >/dev/usb/lp0

And a test coupon with QFP pitch from 0.65 mm to 0.3 mm, discretes from 0603 to 01005, and BGA pitch from 1.0 mm to 0.5 mm:

Background

The web page that got me looking at craft cutters was this one:

http://www.idleloop.com/robotics/cutter/index.php#stencil

These results are very nice, but on the software side I wanted something that fits into a normal PCB workflow with no hassle, by working directly from the solderpaste Gerber file as exported by a PCB CAM tool.

In addition, I wanted the best quality possible. Using the cutter in its default mode rounds off corners considerably due to the drag-knife mechanics, so instead I dice all features into individual line segments and draw them separately in multiple passes. Also, machine backlash is an issue, so the software works around that, at the expense of speed.

Fortunately, the low-level protocol for these machines has been documented, and the rest is mere geometry conversion that's considerably helped by existing tools like gerbv and pstoedit. The software can be found here:

https://github.com/pmonta/gerber2graphtec

Also included are some example Gerber files. A test coupon with QFP/QFN and BGA pitches from 0.65 mm down to 0.3 mm and two-pad footprints from 0603 to 01005 is included, as well as a few larger examples.

The generated files run well on my Silhouette Cameo and probably on other similar Graphtec cutters as well.

Materials

Polyester film is a natural choice. It's inexpensive, dimensionally stable, and very available in the form of laser-printer or copier transparency sheets. Thickness of these sheets is usually around 4 mils, close to the IPC-recommended values for fine-pitch work. Other thicknesses can be obtained easily enough from sources like McMaster-Carr.

I'm using Highland 901 sheets (a 3M brand apparently) together with full-sheet Avery labels, number 5353, as an adhesive backing sheet. The adhesive is a little too aggressive and can be difficult to remove cleanly once the stencil is finished. One can use Goo-Gone or similar citrus-oil cleaner to remove all the adhesive, and this results in a squeaky-clean stencil, but it takes a few minutes of extra time. Perhaps it would be better to use the cutter's cutting mat, though cleaning off the small plastic chads is a bother too. Another option might be to use a separate full-sheet double-sided low-tack adhesive to laminate a plastic sheet to a plain paper backing.

Calibration

Two aspects of the machine should be calibrated for best performance: cutting force and the spatial coordinate system.

For force, the software includes an example script that produces 30 small squares, each cut with a different force. Just have a look at the result to see which force settings result in good performance with your material stackup (mylar plus adhesive backing): first, a reasonable initial cut, to score the material, and second, a final pass that aims to cleanly separate the unwanted material from the stencil background.

For axis calibration, a script is provided to cut a calibration artifact. Measure the distance between marks along each direction (x, y, 45 degrees, and -45 degrees), then calculate a matrix to take out the distortion. (Rub in a bit of felt-tip-pen ink to make the marks more visible when comparing against a good ruler. The provided script produces a 17-step vernier against a 1/16-inch ruler; modify this for 11 steps against a 1 mm ruler if you're using a metric ruler.) My machine is pretty reasonable in x, has a rather large 0.6% error in y, and has a skew of about 1 milliradian. After compensation I think the error is down to less than 0.1%. Even this is uncomfortably high: it is still a 50-micron positioning error across half the dimension of a 100 mm board.

Platform notes

So far I've run this only under Linux (Fedora), which provides a device node at /dev/usb/lp0 when the device is plugged in. Other platforms may need different device-driver arrangments. One can always send the output of gerber2graphtec to a file and deal with getting it to the cutter separately. Fortunately no feedback from the cutter seems to be necessary.

Application notes

Perhaps these stencils are best suited to prototyping that needs very fast turnaround. For example, it's sometimes convenient to populate and test only parts of a board, and for this separate stencils can be cut for each region.

I plan to evaluate at some point this source of laser-cut Kapton stencils:

http://ohararp.com/Stencils.html

as well as the various lower-end laser-cut stainless vendors.

555 contest entries

2011-02-28T12:00:00-05:00

Here are my two entries for the 555 design contest.

An op-amp made from 555 chips

Digital logic using 555 chips

2011-02-27T12:00:00-05:00

Question: is the 555 complete in the Boolean sense? That is, can any Boolean function be realized as a network of 555 chips?

Answer: yes. Tie the threshold pin high---this essentially disables the 555's internal latch. Now provide inputs to the reset and trigger pins and take the output from either the totem-pole output or the open-collector output with a suitable external load. Here is the truth table:

reset	trigger	output
0	0	0
0	1	0
1	0	1
1	1	0

This is a somewhat unusual gate---it can be interpreted as the negation of the conditional operator, or as an AND gate with one of the inputs inverted. But it is complete: an inverter can be obtained by tying reset high; now using this inverter, invert the reset input and one has a NOR gate made from two 555s; the NOR gate is known to be complete. Of course a given Boolean function will be implemented most efficiently by telling the logic synthesis tool (or human designer) to map directly onto the "555 gate" rather than use the NOR-gate construction; but the NOR is a convenient route to the completeness proof.

Storage elements can be made from cross-coupled gates or, as we will see below, from 555s configured to use their internal latch, which is slightly more efficient.

So we immediately have the whole of digital design available to us. One can imagine various projects---counters, state machines, memories, computers---all of which can be built from a large pile of 555s. Of course the same could be said about a large pile of 7400 TTL NAND gates, or transistors. What sorts of constructions, then, should we pursue that would be most interesting from a 555-chip point of view?

It's just my opinion, but it seems best to try to use as much of the 555 internal structure as possible to implement gates and latches efficiently. For combinational logic, we have the raw "555 gate" and the possibility of using a wired-AND connection with the open-collector/open-drain output and a resistor pullup (at the cost of some static power; "NMOS"). For sequential logic, we need to choose a storage element and a clocking scheme. Below is one such choice together with an example circuit: a 2-bit counter and a 7-segment decoder, enough to serve as a proof of principle.

Here is the breadboarded system, together with an annotated picture showing the location of functional blocks. There are a total of 18 556 packages, equivalent to 36 555s.

Video of the system with the clock set to about 2 Hz:

https://youtube.com/shorts/RS2Q634F5OM

Why two-phase clocking rather than edge-triggered logic in the modern style? Well, edge-triggered flip-flops are somewhat trickier to design and verify. A two-phase clock feeding a pair of transparent latches is almost bulletproof. One has complete control over the duration of non-overlap between the two phases (to control skew) as well as the overall frequency of the clock. Even clock glitches can be tolerated (provided there is no crosstalk between the phases), since a single clock phase is idempotent.

This logic technology should have no trouble scaling up to larger systems. I had hoped to do this small 4-bit CPU:

//
// tiny Harvard-architecture 4-bit CPU
//
// February 2011
// Peter Monta
//

module cpu(
  input clk, reset,
  output reg [4:0] pc,       // program counter
  input [7:0] ir,            // instruction
  output [3:0] addr,         // data address
  input [3:0] din,           // data input
  output [3:0] dout,         // data output
  output wr                  // write signal
);

  reg [3:0] a;         // accumulator
  reg c;               // carry flag

  assign addr = ir[3:0];
  assign dout = a;
  assign wr = ir[7:5]==3'b001;

  wire [3:0] b = ir[4] ? ir[3:0] : din;       // data memory or literal
  wire z = a==4'd0;                           // zero flag

  always @(posedge clk)
    if (reset)
      pc = 0;
    else begin
      pc = pc+1;
      case (ir[7:5])
        3'b000: a = b;                     // lda
        3'b001: ;                          // sta
        3'b010: {c,a} = a + b + c;         // adc
        3'b011: a = ~(a|b);                // nor
        3'b100: pc = ir[4:0];              // jmp
        3'b101: if (!c) pc = ir[4:0];      // jnc
        3'b110: if (!z) pc = ir[4:0];      // jnz
        3'b111: c = ir[0];                 // setc
      endcase
    end

endmodule

but there just wasn't time. Its size (after doing the synthesis manually) is 387 555-chips, or 194 packages using the 556. That would need a PCB; it's too big to wire by hand. Here's a PDF of the schematic and the kicad source files.

Possible future directions:

try for some sort of pass-transistor logic by floating a 555's ground pin and using the open-drain FET in a series mode
dynamic latches (with capacitors as storage elements), precharge schemes, DRAM

An op-amp made from 555 chips

2011-02-27T12:00:00-05:00

Is it possible to make an op-amp out of nothing but 555 chips and passive components? Not a terribly practical question, given the existence of very inexpensive and capable op-amps covering every corner of op-amp performance space; but it has some aesthetic appeal. If you find yourself on a desert island with nothing but a pile of 555s and a need for an op-amp, by all means read on.

The 555 has two comparators, but offers direct access to neither. The "trigger" comparator could conceivably work with feedback from the control pin, but the existence of a 2:1 resistive divider in the feedback path is very awkward. And while the "threshold" comparator sees both the input pin and the control pin directly, unfortunately its output can't flow through the digital portion of the 555: the threshold comparator can only reset the RS latch, not set it.

Even if we could use the threshold or trigger comparators directly, they have the disadvantage that one of their inputs is tied to a resistive bias network, resulting in a very low input impedance on that input (in the neighborhood of 30k ohm for the CMOS flavors of the 555; 3k ohm for bipolar). Potentially tolerable for something like a unity-gain buffer, where a low-impedance output drives the input pin, but not good for a general-purpose op-amp.

So instead we can adopt the following approach:

use two 555s, one for each op-amp input, using the high-z threshold pin on each 555
compare the inputs to a common ramp generated by an auxiliary 555, converting voltage to time
use postprocessing logic (implemented with "555 gates") to compare the PWM signals, generate error pulses, and integrate them

The schematic below shows one implementation. I used the TS555 from ST Microelectronics; it is a CMOS 555 with improved specs over the bipolar original.

First, a conventional astable oscillator generates a sawtooth waveform ranging between 1/3 Vcc and 2/3 Vcc. This is fed to the control inputs of two additional 555 chips serving as analog comparators; their outputs encode the op-amp input voltages as PWM waveforms. The digital gates (implemented with 555 chips, of course, as shown at the bottom of the schematic) compare the edges of the PWM waveforms, generating pulses if waveform A is ahead of waveform B or vice-versa. These pulses are integrated with a capacitor, using diodes to isolate the two totem-pole outputs (I suppose one could dispense with the lower diode and use the open-drain 555 pin instead). Ten 555 chips are used in all.

This is all quite similar to a charge-pump PLL. In fact I built the circuit first without the inverter pairs and wound up with some flaky behavior: hysteresis, distorted waveforms, etc. This is because at equilibrium the edges are very close together and the gates cannot generate pulses narrow enough to represent the tiny phase difference. The solution is the same one the PLL chips use: anti-backlash delays. The inverter pairs introduce enough delay so that at equilibrium, pulses are generated in both plus and minus arms, which cancel once they hit the integrating capacitor. And now small PWM edge movements result in linear net charge to the capacitor.

Speaking of PLLs, another possible op-amp implementation would use voltage-to-frequency converters at the inputs, then compare the frequencies with a sequential ("type-IV") phase-frequency detector, again implemented with 555 chips. But besides being more complicated, one might worry about injection locking. I ended up not trying it.

The test circuit is a simple inverting gain-of-10 amplifier:

Here is the breadboarded system:

and a closeup of the breadboard:

This scope trace shows an input of 100 mV peak and an output of about 1 V peak:

Same thing but with square waves; note the asymmetry in the large-signal response between rising and falling edges:

Smaller amplitude signal, 30 mV in, 300 mV out. Note the "fuzz" on the output waveform; these are the high-frequency steps on the output from the error pulses. Low-pass filtering the output attenuates this fuzz and results in a clean waveform:

Finally, here is a low-amplitude square wave as input (about 6 mV peak), still with the low-pass filter on the output. The output is more symmetrical than in the large-signal example. Horizontal scale is 200 microseconds per division.

Despite the low gain-bandwidth product (about 10 kHz), this op-amp might be usable for some low-frequency applications, such as general-purpose amplification, sine-wave oscillators (e.g. Wien bridge or RC phase-shift), active filtering, or even analog computation.

Possible enhancements:

some way to implement chopper stabilization? The lack of a series switch element in the 555 makes this difficult
dead bug or PCB construction for better signal integrity
556 chip for the two comparators for better matching and possibly lower offset
use the discharge pin on the astable to generate a rail-to-rail RC ramp; maybe would result in larger common-mode range
implement an offset nulling network, perhaps by scaling/offsetting one of the control voltages, or using a variable digital delay